This invention relates to a power supply circuit for an amplifier, and more particularly to a power supply circuit for a power amplifier.
To minimize power loss in a power amplifier and to improve power efficiency, the power supply method shown in FIG. 1 has been adopted. In FIG. 1, an input signal v.sub.i is amplified by a voltage amplification stage 1 and applied to a driver stage 3 through a bias stage 2, the driver stage being composed of transistors Q.sub.1, Q.sub.2 and a resistor R.sub.1. The emitter outputs of the driver transistors Q.sub.1, Q.sub.2 become the base inputs of transistors Q.sub.3, Q.sub.4 which constitute an output power stage 4, respectively. The emitter outputs of both transistors Q.sub.3, Q.sub.4 drive a common load R.sub.L in a push-pull stage via resistors R.sub.2, R.sub.3.
Power supply circuits 5 and 6 are provided to supply power to the collector terminals of the output transistors Q.sub.3, Q.sub.4, respectively. In addition, a voltage source .+-.B.sub.1 is provided to generate a constant voltage at a low level. The voltage source .+-.B.sub.1 is used to apply a voltage to the collectors of the output transistors Q.sub.3, Q.sub.4 via unidirectional diodes D.sub.1 and D.sub.2. The power supply circuits shown at 5 and 6 are provided with emitter follower type transistors Q.sub.11, Q.sub.12 and Q.sub.13, Q.sub.14 arranged in a Darlington connection, respectively. The voltage obtained by shifting the level of an amplified output v.sub.o in positive and negative directions by Zener diodes D.sub.3 and D.sub.4 is supplied to the base of the transistors Q.sub.11, Q.sub.13. Power is supplied to the collector of each of the transistors Q.sub.11, Q.sub.12 and Q.sub.13 and Q.sub.14 from supply source .+-.(B.sub.1 B.sub.2) in the circuit to allow them to operate as emitter followers, and a voltage corresponding to the circuit output v.sub.o is supplied to the collector of each of the output transistors Q.sub.3, Q.sub.4. Incidentally, current sources I.sub.1, I.sub.2 are used as operating current sources for the Zener diodes D.sub.3, D.sub.4.
In the power supply circuit thus arranged, when the level of the output signal v.sub.o is low, the diodes D.sub.1, D.sub.2 are simultaneously turned on so that the voltage of circuit supply sources .+-.B.sub.1 can be supplied as a source for the collectors of the output transistors Q.sub.3, Q.sub.4. When the absolute value of the base voltage of the transistors Q.sub.11, Q.sub.13 increases as the level of the output signal v.sub.o rises further, each of the transistors Q.sub.11 -Q.sub.14 conducts and a voltage almost equal to the base voltage of the transistors Q.sub.11, Q.sub.13, that is, the voltage .vertline.v.sub.o +V.sub.Z .vertline., is supplied at each emitter follower output as a power supply for the collector of each of the output transistors Q.sub.3, Q.sub.4. In this case, the Zener voltage V.sub.Z is that present in the Zener diodes D.sub.3, D.sub.4.
Accordingly, when the signal output is small, power is supplied from the lower voltage source and when the signal output becomes larger, a voltage changing according to the signal output is supplied as a power supply. Compared with an arrangement in which power is always supplied from a constant high voltage source, power loss is extremely reduced by this arrangement. FIG. 2 indicates the characteristic of the power loss against the output power; the method of FIG. 1 is shown by the solid line, whereas a method using a constant voltage source is indicated by the dotted line.
Although power efficiency is extremely improved by the circuit arrangement of FIG. 1, the emitter follower with the transistors Q.sub.11 -Q.sub.14 in the power supply circuits 5 and 6 tends to oscillate readily under the influence of the inductance of lead wires and connection cords, the capacitance between electrodes, floating capacitances and the like. Compensation to prevent such oscillation has not been possible. In addition, when a signal having a high frequency component is applied, a time lag occurs in the voltage applied to the collectors of the transistors Q.sub.3, Q.sub.4, allowing the output transistors Q.sub.3, Q.sub.4 to be temporarily saturated and causing the occurrence of output signal distortion.